Optimization of Queueing Performance and Design Variables in a Single-Bus Shared-Memory System − with Application to MPEG-2 Video Decoder System BE ACCEPTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN COMPUTER ENGINEERING

This thesis presents a methodology of decision-making for the design variables, embedded I/O buffer sizes, in a single-bus shared-memory system. The decision is made with the aid of a queueing model, simulation, and an optimization algorithm. A queueing model is used to simulate the system behavior and to obtain the system response. The generalized queueing model is simulated to cover two cases: independent processing units and pipelined processing units in a shared-memory environment. The objective is to obtain the best performance with the optimized embedded buffers in the system. Therefore, an algorithm is developed to find the optimal solution efficiently by exploring the correlation between buffers and system performance. The local optimum is guaranteed. The method can be widely applied to many applications.